In sense amplifier based self-timed memories, two events are crucial for a proper functioning of static random access memories (SRAMs). The first event is a triggering ON of a sense amplifier (SENAMP) when a sufficient differential is developed on bit-lines to read data stored in a bit-cell with a minimum reaction time of the sense amplifier. The other event is a turning OFF of the sense amplifier, when the read data is latched with a safe margin across process, voltage and temperature (PVT) variations. This safe margin can be difficult to achieve across the PVT variations.
It is known that a precharging of internal nodes of the sense amplifier and subsequently, a start of a new cycle, depends on a pulse width of a sense amplifier enable (SAen) signal. Thus, the pulse width of the SAen signal, i.e., resetting of the SAen signal, is crucial for an efficient cycle time.
Generally, the triggering ON of the sense amplifier can be managed through tracking schemes like bit-line tracking approach. However, the turning OFF of the sense amplifier requires some efficient schemes to successfully latch read data without penalizing cycle time across PVT variation.